903 233rd St SE
Bothell, WA 98021

Greg Steiert

425-381-5045
greg@steiert.net

Objective

To find a position that enables me to use my broad technical background to help people solve problems creatively.

Education

California Institute of Technology,
B.S.E.E. 1996

Patents

US Patent #6,122,735, "Fault resilient boot circuit using ring counter"
US Patent #5,790,430, "Variable speed fan failure detector"

Work Experience

Avnet: Redmond, WA; 2008 - Present

Field Applications Engineer:
Presently I am the generalist FAE in the state of Washington. I support customers with products from a variety of suppliers. For the first two years I supported the Maxim product line exclusively. I meet with customers to understand their needs and identify the relevant solutions from the suppliers I support. I also field technical questions and deliver product training.

I have authored a variety of presentations including: Introduction to electronics, Maxim synchronous switching regulators, Maxim system management products, Introduction to stepper motors, and a power selection matrix. I have also created a variety of new product proposals based on customer inquiries.

One major accomplishment has been turning around Maxim's image at a key customer. Working with the local Avnet and Maxim account managers, we were able to improve Maxim's image to the point where they went from being a non-preferred supplier to being recognized as a model partner at the customer's annual supplier conference.

MathStar: Hillsboro, OR; 2007 - 2008

Senior Systems Engineer:
I lead the system level engineering effort to support the companies Field Programmable Object Arrays. I designed boards and systems for validation and demonstration, and helped ASIC customers bring products to market. Since starting, I built up the system engineering infrastructure, including bringing online a PLM engineering database complete with integration to the company's ERP system.

While at MathStar I developed a new validation system built around a network connected microcontroller that allows for monitoring and control of power, clocks, temperature and other configuration settings. This system is very extensible and has greatly improved the automation of the silicon validation effort. The design relied heavily on web standards making it easy to access in any programming language, and allowing for custom user interfaces that could be run in the browser with no software to install.

Omneon Video Networks: Beaverton, OR; 2004 - 2007

Senior Hardware Engineer:
As the senior board designer my duties consisted of all aspects of board design including system architecture, schematic entry, component selection, compliance testing, CPLD/FPGA design, overseeing layout, board stack-up, signal integrity, DFM/DFT, system debug, etc. The boards were designed in a constraint driven process using the Cadence Allegro tool suite.

The products are modular, real-time, multi-processor, hard disk based media servers. They consist of custom X-Scale based embedded servers that manage a RAID file system over Fibre Channel and connect to a variety of codecs over 1394. The systems are designed for high bandwidth and contain a variety of I/O including Fibre Channel, Gigabit Ethernet, 1394, SDI, PCIX and PCI Express. I was also responsible for all the glue logic on the boards. I have written code in Verilog for I2C/SPI controllers, VITC decoder, fan control, interrupt control, FPGA loading, address decoding, and other miscellaneous functions.

Welch Allyn: Beaverton, OR; 2003 - 2004

Electronics Engineer:
Enhanced existing designs on portable medical monitoring products in Product Optimization Group. Most projects were modifying designs to deal with component obsolescence, or manufacturing issues. The products were battery powered portable monitors with microprocessors and very sensitive analog circuitry. Being medical products, there was very rigid process control and a higher level of compliance testing.

Northwest Logic: Hillsboro, OR; 2002 - 2003

Senior Design Engineer:
I worked as a subcontractor. The projects were mostly turn-key board designs where I performed all tasks with the exception of some of the assembly. I did design as well as project management and sales support. Design tasks included schematic capture, layout, and debug. Project management tasks included part and assembly procurement, scheduling and some quote preparation. The projects consisted of a custom active matrix LCD display system with an embedded DSP, and a couple small analog board designs.

Focus Enhancements: Hillsboro, OR; 2001 - 2002

ASIC Design Engineer:
Designed video ASIC's with a small team of engineers. I mainly wrote RTL and test-benches in Verilog for scan converters that reformat VGA for TV. Some of the technologies used include, video scaling, color conversions, NTSC/PAL/HDTV encoding, and closed caption generation. As part of a small team, I also performed many other functions such as writing interactive web pages to enhance efficiency, and designing boards to test the chips. In addition to the Verilog the chips were designed in, I also wrote code in Perl and C to automate the build and test environment.

Geocast Network Systems: Beaverton, OR; 1999 - 2001

Board Design Engineer:
I was one of two board designers at a small start up, and for a period of time, I was the only board design engineer. I have been responsible for all aspects of board design. My main accomplishment was implementing the design of the ATSC receiver. The ATSC receiver consisted of a MIPS based computer with a custom chipset that interfaced the processor and memory to PCI and IDE. The system also contained; PCI Ethernet adapter, USB Ethernet adapter, FPGA, CPLD, PIC micro-controller, and ATSC receiver (tuner, IF down-converter, A/D and demodulator). I also developed an automated system for grading the performance of ATSC demodulators.

Intel Corporation: DuPont, WA/Hillsboro, OR; 1992 - 1999

Board Design Engineer: DuPont, WA; 1997 - 1999
Was responsible for the design of the processor board in a Merced/460GX system. The processor board contained the quad-processor front side bus and the 2 system controller chips, and had connections to the memory and I/O subsystems.

System Design Engineer: Hillsboro, OR; 1996 - 1997
Designed quad-processor server enclosures to comply with thermal, EMC, environmental and regulatory requirements.

Summer Internships: Hillsboro, OR; 1992, 1993, 1994, 1995

California Institute of Technology: Pasadena, CA; 1993 - 1996

Teaching Assistant:
I was a teaching assistant for three introductory electronics classes, 2 of which included labs. I began assisting with the first two classes in only my second year as an undergraduate.